Thursday 17 April 2008
Low-jitter clock generator
Hernan Alcerreca
A multi-rate video clock generator with genlock from National Semiconductor Corp. (NYSE:NSM) delivers high-definition (HD) clock output jitter as low as 40ps peak-to-peak. The LMH1982 provides reference clocks for video analogue-to-digital converters (ADCs), digital-to-analogue converters (DACs) and field-programmable gate array (FPGA) transceivers. These reference clocks ensure a system’s 3Gbps (3G), HD and standard-definition (SD) serial digital interface (SDI) output jitter is in compliance with the Society of Motion Picture and Television Engineers (SMPTE) video standards.
The LMH1982’s 5 x 5mm package size simplifies the design of video cameras, digital recorders and a wide range of video editing and post-production equipment. The LMH1982 can replace discrete and FPGA phase-lock loops (PLLs) with multiple voltage controlled crystal oscillators (VCXOs), while offering total power dissipation of 250mW. Only one external VCXO is required to operate the LMH1982. The device can generate two simultaneous SD and HD output clocks and an output top of frame (TOF) timing pulse. In genlock mode, these output signals can be phase-locked to H and V sync signals applied to either of the reference ports.
The LMH1982’s low-jitter output clocks are capable of driving FPGA serialisers without the need for additional clock cleansing. The device’s integrated PLLs can synchronize the output clocks to an analog timing reference from National’s LMH1981 multi-format video sync separator or a digital timing reference from an SDI deserializer. The use of an external loop filter offers additional configurability to optimize rejection of reference input timing jitter.
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